Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. There are a number of types of semiconductor imagers, including charge coupled devices, photodiode arrays, charge injection devices, and hybrid focal plane arrays. Some sensors are referred to as active pixel image sensors (APS). An active pixel image sensor is defined as an image sensor technology that has one or more active transistors within the pixel unit cell. Some types of active pixel sensor technologies include the amplified MOS imager (AMI), charge modulation device (CMD), volt charge modulated device (VCMD), base stored image sensor (BASIS), and the static induction transistor (SIT).
One prior art circuit using a CMOS photodiode-type active pixel sensor is shown in “128×128 CMOS Photodiode-Type Active Pixel Sensor With On-Chip Timing, Control And Signal Chain Electronics,” by R. H. Nixon et al., Proceedings of the SPIE-The International Society for Optical Engineering, Volume 2415, 1995, pages 117-123. FIG. 2 of that reference has been reproduced herein as FIG. 1.
FIG. 1 is a schematic diagram of a CMOS APS, along with readout circuits. The pixel unit cell 25 consists of a photodiode (PD), a source-follower input transistor SF1, a row-selection transistor ROW and a reset transistor RESET which controls lateral blooming through proper biasing of its gate. The drain diffusion 50 is coupled to the voltage source VDD. At the bottom of each column of pixels, there is a column circuit 60 consisting of a load transistor VLN1 and two output branches to store the reset and signal levels. Each branch consists of a sample and hold capacitor (CS or CR) with a sampling switch (SHS or SHR) and a second source-follower SF2 with a column-selection switch (COL). The reset and signal levels are read out differentially, allowing correlated double sampling to suppress 1/f noise and fixed pattern noise (not kTC noise) from the pixel. A double delta sampling (DDS) circuit shorts the sampled signals during the readout cycle reducing column fixed pattern noise. These readout circuits 60 are common to an entire column of pixels. A read-out circuit 70 that is common to the entire array includes load transistors (VLN2) of the second set of source followers (VLP) and the subsequent clamp circuits CLAMP and output source followers SF3 and SF4.
Timing for the readout sequence is as follows. After a row has been selected, the signal that is present on each column pixel in that row is sampled (SHS) onto the holding capacitor CS. Next, each pixel in the row is reset (RESET). This is followed by sampling the reset level (SHR) onto holding capacitor CR. A simplified expression for the output voltage of the reset branch of the column circuit is given by:Vcol—R≅β{α[Vpdr−Vtpix]−Vtcolr}
where α is the gain of the pixel source-follower, β is the gain of the column source-follower, Vpdr is the voltage on the photodiode after reset, Vtpix is the threshold voltage of the pixel source-follower n-channel transistor, and Vtcolr is the threshold voltage of the column source-follower p-channel transistor. Similarly, the output voltage of the signal branch of the column circuit is given by:Vcol—S≅β{α[Vpds−Vtpix]−Vtcols}
where Vpds is the voltage on the photodiode with the signal charge present and Vtcols is the threshold voltage of the column source-follower p-channel transistor. Experimentally, the peak to peak variation in Vtcolr−Vtcols is typically 10-20 mV. It is desirable to remove this source of column-to-column fixed pattern noise FPN. JPL has previously developed a double delta sampling (DDS) technique to eliminate the column-to-column FPN. This approach represents an improved version of the DDS circuitry.
Sequential readout of each column is as follows. First a column is selected. After a settling time equivalent to one-half the column selection period, the DDS is performed to remove column fixed pattern noise. In this operation, a DDS switch and two column selection switches on either side are used to short the two sample and hold capacitors CS and CR. Prior to the DDS operation the reset and signal column outputs (Vcol_R and Vcol_S) contain their respective signal values plus a source follower voltage threshold component. The DDS switch is activated immediately after CLAMP is turned off. The result is a difference voltage coupled to the output drivers (VR_OUT and VS_OUT) that is free of the voltage threshold component.
One problem of this circuit is that the implementation of the active pixel cell 25 continues to have the problems related to the design choice between hard reset and soft reset implementations. The choice between these implementations determine how the reset signal RST and the voltage on the drain diffusion 50 (hereafter designated as VRST) will be controlled. In the implementation illustrated in FIG. 1, a soft reset implementation is shown, in that the voltage VRST on the drain diffusion 50 is shown to be VDD. This is a typical prior art implementation in which VRST=VDD=RST. One definition of a soft reset system is where the signal (shown as VDD on the drain diffusion 50 in FIG. 1) is greater than the reset voltage RST, minus a threshold voltage VT. This soft reset definition is illustrated in the equation:soft reset: VRST>RST−VT  (1)where the threshold voltage VT is a variable, depending on sensor potential. Also, the theoretical equation for the noise in a soft reset system is:
                              soft          ⁢                                          ⁢          reset          ⁢                      :                    ⁢                                          ⁢          Noise                =                              1            2                    ⁢                                    KT              C                                                          (        2        )            
In contrast, one definition of a hard reset system is where the VRST level is less than the reset signal RST minus the threshold voltage VT. This hard reset definition is illustrated in the equation:hard reset: VRST<RST−VT  (3)
And the theoretical equation for the noise in the hard reset method is:
                              hard          ⁢                                          ⁢          reset          ⁢                      :                    ⁢                                          ⁢          Noise                =                              KT            C                                              (        4        )            
The hard reset and soft reset equations (1) and (3) illustrate that there is a critical voltage VCR which marks the boundary between a soft reset and a hard reset. This critical voltage is defined by the equation:critical voltage: VCR=RST−VT  (5)
The advantages of the hard reset method is that it is fast and uniform, but in theory it suffers from approximately twice the reset noise problems (kTC noise) of the soft reset method. In contrast, the soft reset method has less reset noise, but causes image lag, because the reset is incomplete due to the reset transistor operating in the subthreshold region.
The present invention is directed to a method and apparatus that overcome the foregoing and other disadvantages. More specifically, the present invention is directed to a method and apparatus for reducing image lag through an improved soft reset circuit for an active pixel sensor (APS).